System and method for address broadcast synchronization using a plurality of switches

ABSTRACT

A system and method providing address broadcast synchronization using multiple switches. The system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch. The second switch selects a selected address request, and the first and the second switch are further configured to broadcast concurrently a corresponding address to the selected address request. A method is also contemplated for concurrently providing addresses to a plurality of devices. A method of arbitrating in a first switch and a second switch between requests to the first switch and the second switch is disclosed where the arbitrated outcomes in both the first switch and the second switch are identical.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to cache synchronization, and moreparticularly to address broadcast synchronization to a plurality ofpotentially responding devices.

[0003] 2. Description of the Relevant Art

[0004] Maintaining cache coherency in an N-way system, where N is thenumber of processors in the system, is essential. In a system where N issmall (N<4), the address buses of all cacheable devices may bephysically connected together. Therefore, all cacheable devices may seea cache miss address simultaneously. On the other hand, when a system ofN is large (N>4), it becomes electrically unfeasible to connect theaddress buses of all cacheable devices together.

[0005] One approach for achieving cache coherency in a system with largeN, is by broadcasting the cache miss addresses to all cacheable devicessimultaneously, through an address broadcast network. The addressbroadcast network has an address-in and an address-out connection toeach of the cacheable devices. When a device sends a cache miss addressto the address broadcast network, the address gets buffered, and thenbroadcast to all devices concurrently, so that all devices may check orupdate their tags appropriately.

[0006] One problem with building an address network in hardware forlarge systems (N>4) is that one needs a very large pin count ASIC(Application Specific Integrated Circuit) to accommodate all address-insand address-outs for all cacheable devices to maintain addresssynchronization. The expense of building a large pin count ASIC toaccommodate all address-ins and all address-outs for all cacheabledevices limits this solution to only a very small number of computersystems.

[0007] Another possible solution is to slice the address network into X(X>1) slices for a small ASIC solution. The problem with address slicingis that using typical request and grant flow control techniques betweenaddress slices to maintain address synchronization requires a computersystem performance degradation that is unacceptable.

[0008] What is needed is a mechanism for achieving synchronizationbetween address network slices without substantial performancedegradation. The request and grant flow control technique used shouldrequire a minimum number of control signals passing between each switch.

SUMMARY OF THE INVENTION

[0009] The problems outlined above are in large part solved by a systemand method providing address broadcast synchronization using multipleswitches. Each switch may be an application specific integration circuit(ASIC) or a separate switching device. By dividing address requestsbetween more than one switch, addresses may be broadcast concurrently toa plurality of devices, which may advantageously provide for a highersystem performance at a lower cost.

[0010] In one embodiment, the system for concurrently providingaddresses to a plurality of devices includes a first switch and a secondswitch. The first switch is coupled to receive address requests from afirst plurality of sources. The first switch is configured to output theaddress request from the first plurality of sources. The second switchis coupled to receive address requests from a second plurality ofsources. The second switch is configured to receive the address requestfrom the first plurality of sources from the first switch. The secondswitch is further configured to delay the address request from thesecond plurality of sources prior to arbitrating between ones of theaddress request from the second plurality of sources and ones of theaddress request from the first party of sources received from the firstswitch. The second switch selects a selected address request, and thefirst and the second switch are further configured to broadcastconcurrently a corresponding address to the selected address request.

[0011] A method is also contemplated, in one embodiment, forconcurrently providing addresses to a plurality of devices. In oneembodiment, the method comprises receiving at a first switch a firstaddress and a corresponding first request from a first device. Themethod receives at a second switch a second address and a correspondingsecond request from a second device, with the first switch beingdifferent from the second switch. The method transfers the secondaddress and the corresponding second request to the first switch. Themethod delays the corresponding first request in the first switch. Themethod arbitrates in the first switch between the corresponding firstrequest and the corresponding second request but rather the firstaddress or the second address will comprise a first transmission. Themethod concurrently broadcasts to a plurality of devices the firsttransmission from the first switch and the first transmission from thesecond switch where the first transmission from the first switch and thefirst transmission from the second switch are identical.

[0012] In another embodiment, a system for concurrently providingaddresses to a plurality of devices includes a first switch and a secondswitch. The first switch is coupled to receive address requests from afirst plurality of sources. The first switch is configured to output theaddress request from the first plurality of sources. The second switchis coupled to receive address requests from a second plurality ofsources. The second switch comprises a broadcast buffer, an incomingbuffer, a delay circuit, and a broadcast arbiter. The broadcast bufferis coupled to receive addresses of the address requests from the secondplurality of sources. The incoming buffer is coupled to receiveaddresses of the output of the address requests from the first pluralityof sources from the first switch. The delay circuit is coupled toreceive the address requests from the second plurality of sources. Thedelay circuit is configured to delay the address requests from thesecond plurality of sources for a predetermined length of time. Thebroadcast arbiter is coupled to arbitrate between ones of the addressrequest from the second plurality of sources and ones of the output ofthe address request from the first plurality of sources from the firstswitch for a selected address request. The first switch and the secondswitch are further configured to broadcast concurrently a correspondingaddress to the selected address request selected in the broadcastarbiter.

[0013] In still another embodiment, a method of arbitrating in a firstswitch and a second switch between requests to the first switch and thesecond switch is disclosed. The comprises tracking which switch was mostrecently selected and tracking which switch is next to be selected. Inresponse to a reset, the method selects the first switch and indicatesthat the second switch is next to be selected. In response to only alocal request to the first switch or only a remote request to the secondswitch, the method selects the first switch and indicates that the firstswitch is next to be selected. In response to only a local request tothe second switch or only a remote request to the first switch, themethod selects the second switch and indicates that the second switch isnext to be selected. In response to both a local request and a remoterequest concurrently, the method selects the switch which was not mostrecently selected, and the method indicates that the switch not mostrecently selected will be the next to be selected. Otherwise, the methodselects the first switch and indicates the switch most recently selectedas the next to be selected.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Other objects and advantages of the invention will becomeapparent upon reading the following detailed description and uponreference to the accompanying drawings in which:

[0015]FIG. 1 is a block diagram of an embodiment of a computer systemincluding two switches that concurrently provide addresses to aplurality of devices;

[0016]FIG. 2 is a block diagram of an embodiment of the two switchesshown in FIG. 1; and

[0017]FIGS. 3A and 3B are a flowchart of an embodiment of a method forarbitrating in a first switch and a second switch between request to thefirst switch and the second switch.

[0018] While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and will herein be described in detail. Itshould be understood, however, that the drawings and detaileddescription thereto are not intended to limit the invention to theparticular form disclosed, but on the contrary, the intention is tocover all modifications, equivalents and alternatives falling within thespirit and scope of the present invention as defined by the appendedclaims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Similar features are designed herein using identical referencenumerals. It is noted that the use of a reference numeral with anadditional letter may designate a particular one of a group that mayreferenced as a while with the reference numeral by itself.

[0020]FIG. 1—Computer System Including Two Switches

[0021]FIG. 1 is a block diagram of a computer system including twoswitches, switch 110A and switch 110B. As shown, the computer systemincludes CPUs 115A-115H, input and output devices (I/O) 120A-120D, andmemories 125A-125D. Data signals beginning with a P have a processor 115as a destination, and data signals beginning with an I/O have an I/Odevice 120 as a destination. Switches 110A and 110B are shown receivinginput from various groupings of the processors 115 and the I/O devices120. The switches 110A and 110B are also shown outputting signals tovarious ones of the processors 115, the I/O devices 120, and to thememories 125.

[0022] A plurality of processors (CPUs) 115A-115H (eight as shown), eachreceives an input, preferably addresses, appropriately referenced asP0-P7. Each of the processors 115A-115H outputs an output, preferably anaddress and an address request, such as an address request packet, toone of the two switches 110A and 110B. As shown, switch 110A alsoaccepts address request packets from I/O device 120A and I/O device120B. Also as shown, switch 110B accepts address request packets fromI/O device 120C and I/O device 120D. Switch 110A outputs an outputsignal, preferably address signals, to the CPUs 115A-115D, the I/Odevices I/O0-I/O1, and memories 125A-125B. Switch 110B outputs an outputsignal, preferably address signals, to processors 115E-115H, I/O devicesI/O2-I/O3, and memories 125C-125D. Switch 110A and switch 110B alsoexchange data, preferably including addresses and address requests.

[0023] It is noted that while a particular number of processors 115, I/Odevices 120, and memories 125 are illustrated, any number of processors,I/O devices, and/or memories, or other devices are contemplated. It isalso noted that while unidirectional data paths are illustrated,bi-directional data paths may also be used as desired.

[0024]FIG. 2—Address Broadcast Synchronization Switches

[0025]FIG. 2 is a block diagram of one embodiment of the switches 110Aand 110B. As shown, each switch 110 includes a plurality of input FIFOs(First-In, First Out buffers) 205, a request arbiter 215, an inputmultiplexer (MUX) 210, a broadcast FIFO 225, an incoming FIFO 230, adelay circuit 235, a broadcast arbiter 240, and an output MUX 245. Theswitches 110 exchange output requests from their respective requestarbiters 215 and output addresses from their respective input MUXes 210.

[0026] As illustrated, switch 110A accepts addresses P0P3 and I/O0-I/O1,as well as address requests P0_req-P3_req and I/O0_req and I/O1_req.Switch 110A outputs address signals P0-P3, I/O0-I/O1, and M0-M1. Eachincoming address P0-P3 and I/O0-I/O1 is received into an input FIFO205A-205F. The address requests that correspond to the addressesreceived in the input FIFOs 205A-205F are received at a request arbiter215A. In the preferred embodiment, the request arbiter 215A is around-robin arbiter, although any other means of arbitration may be usedas desired for choosing requests received by request arbiter 215A. Whenthe request arbiter 215A chooses (or arbitrates) for a particularaddress request, the request arbiter 215A controls the selection atinput MUX 210A with regard to the output of the input FIFOs 205A-205F.The selected address request is output as SW0_req to delay circuit 235A.The output of input MUX 210A, shown as signal 220A, is provided to abroadcast FIFO 225A. It is noted that output signal 220A is alsoprovided to switch 110B, and that the address request SW0_req is alsoprovided to switch 110B.

[0027] Switch 110A is also coupled to receive the address requestSW1_req from switch 110B, as well as address output signal 220B. Signal220B is received at incoming FIFO 230A. As shown, broadcast FIFO 225Aand incoming FIFO 230A each output data to output MUX 245A, broadcastFIFO 225A as ‘0’ (zero) and incoming FIFO 230A as ‘1’ (one). Addressrequest SW0_req is delayed for a period of time in delay circuit 235Abefore being provided to broadcast arbiter 240A. The period of time ofthe delay may be a predetermined period of time. It is noted that in apreferred embodiment, the predetermined period of time is equal to thetime required for switch 110A to receive the address request SW1_req andthe address output signal 220B. Broadcast arbiter 240A chooses (orarbitrates) between request SW1_req and request SW1_req. The broadcastarbiter 240A controls the output of output MUX 245A choosing between ‘0’and ‘1’. The output of output MUX 245A, the selected address for thefirst transmission, is provided concurrently to various groups of theprocessors 115, I/O devices 120, and/or memories 125 through signalsP0-P3, I/O0-I/O1, and M0-M1.

[0028] As illustrated, switch 110B accepts addresses P4-P7 andI/O2-I/O3, as well as address requests P4_req-P7_req and I/O2_req andI/O3_req. Switch 110B outputs address signals P4-P7, I/O2-I/O3, andM2-M3. Each incoming address P4-P7 and I/O2-I/O3 is received into aninput FIFO 205G-205L. The address requests that correspond to theaddresses received in the input FIFOs 205G-205L are received at arequest arbiter 215B. In the preferred embodiment, the request arbiter215B is a round-robin arbiter, although any other means of arbitrationmay be used as desired for choosing requests received by request arbiter215B. When the request arbiter 215B chooses (or arbitrates) for aparticular address request, the request arbiter 215B controls theselection at input MUX 210B with regard to the output of the input FIFOs205G-205L. The selected address request is output as SW1_req to delaycircuit 235B. The output of input MUX 210B, shown as signal 220B, isprovided to a broadcast FIFO 225B. It is noted that output signal 220Bis also provided to switch 110A, and that the address request SW1_req isalso provided to switch 110A.

[0029] Switch 110B is also coupled to receive the address requestSW0_req from switch 110A, as well as address output signal 220A. Signal220A is received at incoming FIFO 230B. As shown, broadcast FIFO 225Band incoming FIFO 230B each output data to output MUX 245B, broadcastFIFO 225B as ‘1’ (one) and incoming FIFO 230B as ‘0’ (zero). Addressrequest SW1_req is delayed for a period of time in delay circuit 235Bbefore being provided to broadcast arbiter 240B. The period of time ofthe delay may be a predetermined period of time. It is noted that in apreferred embodiment, the predetermined period of time is equal to thetime required for switch 110B to receive the address request SW0_req andthe address output signal 220A. Broadcast arbiter 240B chooses (orarbitrates) between request SW1_req and request SW1_req. The broadcastarbiter 240B controls the output of output MUX 245B choosing between ‘0’and ‘1’. The output of output MUX 245B, the selected address for thefirst transmission, is provided concurrently to various groups of theprocessors 115, I/O devices 120, and/or memories 125 through signalsP4-P7, I/O2-I/O3, and M2-M3.

[0030] It is noted that the delay circuits 235A and 235B may include anycircuit that is configured to delay the output of a received signal. Inone embodiment, a delay circuit 235 delays the received signal longerthan the minimum time required to propagate the received signal throughdelay circuit 235. In another embodiment, delay circuit 235 includes oneor more flip-flops. It is also noted that in various embodiments variousincoming and outgoing signals to and from switches 110A and 110B may bebuffered at input to the switch 110 and/or on output from the switch110.

[0031] Generally speaking, the system of FIG. 1 operates as describedherein. The first switch 110A is coupled to receive address requestsfrom a first plurality of sources. For example, one plurality of sourcesmay be processors 115A-115D and/or I/O devices 120A-120B. The firstswitch 110A is configured to output a received address request from thefirst plurality of sources.

[0032] The second switch 110B is coupled to receive address requestsfrom a second plurality of sources. For example, the second plurality ofsources may include processors 115E-115H and/or I/O devices 120C-120D.Switch 110B is also configured to receive the address request from thefirst plurality of sources from the first switch 110A. The second switchis further configured to delay internally address requests from thesecond plurality of sources. It is noted that the length of the delaymay be predetermined, and is preferably equal in length of time to thetime delay in receiving the address request from the first plurality ofsources from the first switch. The second switch 110B is furtherconfigured to arbitrate between ones of the address requests from thesecond plurality of sources and ones of the address request from thefirst plurality of sources output from the first switch. The arbitrationbetween the address requests is to determine a selected address request.Once a selected address request has been selected, the first switch andthe second switch are further configured to broadcast concurrently thecorresponding address to the selected address request. It is noted thatthe corresponding address will broadcast to any or all devices,including the CPUs 115A-115H, I/O devices 120A-120B, and memories125A-125D.

[0033] In one embodiment, the second switch 110B is further configuredto output the address request from the second plurality of sources, andthe first switch 110A is further configured to receive this request fromthe second plurality of sources. First switch 110A is further configuredto delay internally the address request from the first plurality ofsources. The time of the delay of the address request from the firstplurality of sources may be a predetermined length of time and ispreferably a length of time approximately equal to the time required forthe second switch 110B to provide the address request in the secondplurality of sources to first switch 110A. The first switch is furtherconfigured to arbitrate between ones of the address request from thefirst plurality of sources and ones of the address requests from thesecond plurality of sources from the second switch. The arbitration isto determine the selected address request, as noted above for the secondswitch 110B. It is noted that the selected address provided by the firstswitch 110A and the selected address provided by the second switch 110Bare the same and are concurrently provided to the devices as describedabove.

[0034] FIGS. 3A-3B—Arbitration by a Broadcast Arbiter

[0035]FIGS. 3A and 3B illustrate a flowchart of an embodiment of amethod for operating an arbiter, such as broadcast arbiters 240A and240B. The method tracks which switch was most recently selected, and themethod also tracks which switch is next to be selected. At decisionblock 305, the method checks to see if reset has been asserted. If resethas been asserted in decision box 305, then an output MUX selects output‘0’ (i.e. switch 110A) and the next granted switch will be the otherswitch (i.e. switch 110B) (step 310).

[0036] If reset has not been asserted in decision block 305, then themethod determines if only a local request has been made to the firstswitch 110A or only a remote request has been made to the second switch110B in decision block 315. If only a local request has been made to thefirst switch 110A or only a remote request is made to the second switch110B, then the method selects output MUX output ‘0’ and the next grantedswitch will be the same switch (step 320).

[0037] If there has not been only a local request to the first switch110A or only a remote request to the second switch 110B, then the methodmoves to decision block 325. If only a local request has been made tothe second switch 110B or only a remote request has been made to thefirst switch 110A in decision box 325, then the method selects outputMUX output ‘1’ and the next granted switch will be the same switch (step330).

[0038] If only a local request to the second switch 110B or only a localrequest to the first switch 110A has not been made in decision block325, then the method moves to decision block 335. In decision block 335,if both a local request and a remote request have concurrently beenmade, and the current granted switch is switch 110A, then the output MUXselects ‘1’ and the next granted switch is switch 110A (step 340). If indecision block 335 both the local request and remote request have beenmade concurrently but the current granted switch is not switch 0, thenthe method moves to decision block 345.

[0039] In decision block 345, if both the local request and a remoterequest have been made concurrently and the current granted switch isswitch 110B, then the output MUX selects ‘0’ and the next granted switchis switch 110A (step 350). It is noted that in decision blocks 335 and345, an affirmative decision is made in either case when a local requestand a remote request have both been made concurrently. In either casethe selected output MUX output is to the switch not most recentlyselected and the indicated switch as the next granted switch is also theswitch not most recently selected.

[0040] The default action when all decision blocks are negative, is forthe outgoing MUX to select ‘0’, and the next granted switch is thecurrent granted switch (step 355).

[0041] In various embodiments, the switches 110A and 110B may beapplication specific integrated circuits ASCIC0 and ASCIC1. In oneembodiment, ASCIC0 and ASCIC1 are location strapped via jumpers. It isnoted that ASCIC0 preferably will have a pull-up resistor, while ASIC1preferably has a pull-down resistor, both of which get latched on resetto identify which is ASCIC0 and which is ASCIC1. Note that the prioritytoggles between the broadcast arbiters based on the switch that had thelast request granted and the current outstanding request. The methoddisclosed may advantageously ensure that both arbiters are synchronizedto each other without a need for request/grant flow control mechanismsbeyond the address and the corresponding address request that wasinitially received.

[0042] As an example of an embodiment of the operations of switches 110Aand 110B, right after a reset, both processors 115A and 115E have anoutstanding address packet in the address network. The P0 address packetis received in switch 110A's input FIFO 205A from processor 115A,whereas the P4 address packet is received and stored in switch 110B'sinput FIFO 205G from processor 115E. The request arbiter 215A in switch110A will receive the P0 request associated with the address stored ininput FIFO 205A. Similarly, request arbiter 215B receives the P4_reqaddress request associated with the P4 address stored in input FIFO205G.

[0043] Request arbiter 215A in switch 110A controls input MUX 210A tooutput the address associated with input signal P0 as output signal220A, which is provided to broadcast FIFO 225A and to incoming FIFO230B. Likewise, request arbiter 215B controls input MUX 210B to outputthe address from P4 as output signal 220B. Output signal 220B isprovided to broadcast FIFO 225B and also to incoming FIFO 230A.Concurrently with the addresses being routed from the input FIFO 205 tothe broadcast FIFOs 225 and incoming FIFOs 230, switch 110A has assertedSW0_req line indicating the presence of an address from switch 110A inbroadcast FIFO 225A and incoming FIFO 230B.

[0044] As a finite amount of time is required for the address and therequest line to be provided from one switch 110 to the other switch 110,in this case from switch 110A to switch 110B, signal SW0_req is firstprovided to a delay circuit 235A, before being provided to broadcastarbiter 240A. In the preferred embodiment, the delay circuit 235A delaysthe address request SW1_req by approximately an equal amount of time asrequired for switch 110A to receive the address and correspondingaddress request from switch 110B. In this embodiment, broadcast arbiter240A receives notice that an address is present in the broadcast FIFO225A concurrently with an address being available in the incoming FIFO230A. The broadcast arbiter 240A chooses (or arbitrates) for prioritybetween the SW0_req and SW1_req. The preferred arbitration method isdescribed above with respect to FIGS. 3A and 3B. Broadcast arbiter 240Aselects either ‘0’ or ‘1’ denoting the address from switch 110A orswitch 110B, respectively, in controlling the output of the outputmultiplexer 245A.

[0045] It is noted that since SW1_req and SW1_req are both required tocross from one switch to the other, the signals endure a delay, such astwo clock cycles in one embodiment. Therefore, each switch 110A and 110Bdelays the address request that it sends, SW0_req and SW1_req,respectively, to the broadcast arbiter 240 of the other switch by anequivalent time period of 2 clock cycles. This delay ensures that thebroadcast arbiters 240A and 240B in each switch 110A and 110B receivethe address request concurrently.

[0046] Switch 110A has the P0 address placed in its broadcast FIFO 225Aand the P4 address placed in incoming FIFO 230A. Switch 110B has the P0address placed in its incoming FIFO 230B and P4 packet placed inbroadcast FIFO 225B. At this time broadcast arbiter 240A has receivedaddress request SW0_req and address request SW1_req, whereas broadcastarbiter 240B has likewise received address request SW1_req and addressrequest SW1_req.

[0047] The arbitration method described above with respect to FIGS. 3Aand 3B illustrates a preferred embodiment of how the broadcast arbiter245 works for each address request that it receives. After a reset, thelast granted switch defaults to switch 110A, so that switch 110Abroadcast arbiter now has the highest priority. When the broadcastarbiter 240A has highest priority, then both broadcast arbiter 240A andbroadcast arbiter 240B will select the ‘0’ of the multiplexer 245B. Itis noted that both broadcast arbiter 240A and broadcast arbiter 240B areat decision block 345 of FIG. 3B. Both a local request and a remoterequest have been received and the current granted switch is switch 110B(the default upon a reset), therefore the output MUXes 245A and 245Bboth select ‘0’ and the next granted which will be switch 110A (step350). Thus, the address from P0 is provided as output 250A and output250B, concurrently on address lines P0-P7, I/O0-I/O3, and M0-M3.

[0048] Continuing, at decision block 325, as the request is now only therequest from switch 1110B, the output MUXes 245 will select ‘1’ and thenext granted will be switch 110B (step 330). It is noted that broadcastarbiter 240A and broadcast arbiter 240B, following an arbitration methodsimilar to that disclosed in FIGS. 3A and 3B, make selections betweenlocal and remote requests which are identical in all cases. It is alsonoted the broadcaster arbiter 240A knows that upon a reset that it willhave priority just as broadcast arbiter 240B knows that after a reset itwill not have priority.

[0049] Numerous variations and modifications will become apparent tothose skilled in the art once the above disclosure is fully appreciated.It is intended that the following claims be interpreted to embrace allsuch variations and modifications.

What is claimed is:
 1. A system for concurrently providing addresses toa plurality of devices, comprising: a first switch coupled to receiveaddress requests from a first plurality of sources, wherein said firstswitch is configured to output said address requests from said firstplurality of sources; and a second switch coupled to receive addressrequests from a second plurality of sources, wherein said second switchis configured to receive said address requests from said first pluralityof sources from said first switch; wherein said second switch is furtherconfigured to delay said address requests from said second plurality ofsources, wherein said second switch is further configured to arbitratebetween ones of said address requests from said second plurality ofsources and ones of said output of said address requests from said firstplurality of sources from said first switch for a selected addressrequest; and wherein said first switch and said second switch arefurther configured to broadcast concurrently a corresponding address tosaid selected address request.
 2. The system of claim 1, wherein saidsecond switch is further configured to output said address requests fromsaid second plurality of sources, and wherein said first switch isfurther configured to delay said address requests from said firstplurality of sources, wherein said first switch is further configured toarbitrate between ones of said address requests from said firstplurality of sources and ones of said address requests from said secondplurality of sources from said second switch for said selected addressrequest.
 3. A system for concurrently providing addresses to a pluralityof devices, comprising: a first switch coupled to receive addressrequests from a first plurality of sources, wherein said first switch isconfigured to output said address requests from said first plurality ofsources; and a second switch coupled to receive address requests from asecond plurality of sources, wherein said second switch comprises: abroadcast buffer coupled to receive addresses of said address requestsfrom said second plurality of sources; an incoming buffer coupled toreceive addresses of said output of said address requests from saidfirst plurality of sources from said first switch; a delay circuitcoupled to receive said address requests from said second plurality ofsources, wherein said delay circuit is configured to delay said addressrequests from said second plurality of sources for a predeterminedlength of time; a broadcast arbiter coupled to arbitrate between ones ofsaid address requests from said second plurality of sources and ones ofsaid output of said address requests from said first plurality ofsources from said first switch for a selected address request; whereinsaid first switch and said second switch are further configured tobroadcast concurrently a corresponding address to said selected addressrequest in said broadcast arbiter.
 4. The system of claim 3, whereinsaid second switch is further configured to output said address requestsfrom said second plurality of sources, wherein said first switch furthercomprises: a first broadcast buffer coupled to receive addresses of saidaddress requests from said first plurality of sources; a first incomingbuffer coupled to receive addresses of said output of said addressrequests from said second plurality of sources from said second switch;a first delay circuit coupled to receive said address requests from saidfirst plurality of sources, wherein said delay circuit is configured todelay said address requests from said first plurality of sources for afirst predetermined length of time; and a first broadcast arbitercoupled to arbitrate between ones of said address requests from saidfirst plurality of sources and ones of said output of said addressrequests from said second plurality of sources from said second switchfor said selected address.
 5. The system of claim 4, wherein said firstpredetermined length of time corresponds approximately to said length oftime for said addresses of said output of said address requests fromsaid second plurality of sources from said second switch to arrive atsaid first incoming buffer.
 6. The system of claim 5, wherein saidpredetermined length of time and said first predetermined length of timeare approximately equal.
 7. The system of claim 4, wherein said firstswitch further comprises: a plurality of first input buffers coupled toreceive said addresses of said address requests from said firstplurality of sources; a first input multiplexer coupled to receive saidaddresses of said address requests from said plurality of first inputbuffers, and wherein said first input multiplexer is further configuredto output a first selected input address to said first broadcast buffer;and a first request arbiter coupled to receive said correspondingrequest addresses of said address requests from said first plurality ofsources, wherein said first request arbiter is configured to arbitratefor said first selected input address, and wherein said first requestarbiter is further configured to control said first input mutliplexer toselect said first selected input address, wherein said first requestarbiter is further configured to output said corresponding requestassociated with said first selected input address to said first delaycircuit.
 8. The system of claim 3, wherein said predetermined length oftime corresponds approximately to a length of time for said addresses ofsaid output of said address requests from said first plurality ofsources from said first switch to arrive at said incoming buffer.
 9. Thesystem of claim 3, wherein said second switch further comprises: aplurality of input buffers coupled to receive said addresses of saidaddress requests from said second plurality of sources; an inputmultiplexer coupled to receive said addresses of said address requestsfrom said plurality of input buffers, and wherein said input multiplexeris further configured to output a selected input address to saidbroadcast buffer; and a request arbiter coupled to receive saidcorresponding request addresses of said address requests from saidsecond plurality of sources, wherein said request arbiter is configuredto arbitrate for said selected input address, and wherein said requestarbiter is further configured to control said input mutliplexer toselect said selected input address, wherein said request arbiter isfurther configured to output said corresponding request associated withsaid selected input address to said delay circuit.
 10. The system ofclaim 3, wherein said plurality of devices includes one or moreprocessors and one or more memories.
 11. The system of claim 10, whereinsaid plurality of devices further includes one or more input/outputdevices.
 12. A method for concurrently providing addresses to aplurality of devices, the method comprising: receiving at a first switcha first address and a corresponding first request from a first device;receiving at a second switch a second address and a corresponding secondrequest from a second device, wherein said second switch is differentfrom said first switch; transferring said second address and saidcorresponding second request to said first switch; delaying saidcorresponding first request in said first switch; arbitrating in saidfirst switch between said corresponding first request and saidcorresponding second request for whether said first address or saidsecond address will comprise a first transmission; and concurrentlybroadcasting to a plurality of devices said first transmission from saidfirst switch and said first transmission from said second switch,wherein said first transmission from said first switch and said firsttransmission from said second switch are identical.
 13. The method ofclaim 12, further comprising: transferring said first address and saidcorresponding first request to said second switch; delaying saidcorresponding second request in said second switch; and arbitrating insaid second switch between said corresponding first request and saidcorresponding second request for whether said first address or saidsecond address will comprise said first transmission.
 14. The method ofclaim 13, further comprising: buffering said first address at said firstswitch prior to said transferring said first address; and buffering saidsecond address at said second switch prior to said transferring saidsecond address.
 15. The method of claim 13, further comprising:buffering said first address at said first switch prior to saidarbitrating in said first switch; and buffering said second address atsaid second switch prior to arbitrating in said second switch.
 16. Themethod of claim 13, further comprising: buffering said first address atsaid second switch prior to said arbitrating in said second switch; andbuffering said second address at said first switch prior to arbitratingin said first switch.
 17. The method of claim 13, further comprising:receiving at said first switch another address and a correspondinganother request from another device; buffering said another address atsaid first switch prior to said transferring said first address; andarbitrating between said corresponding first request and saidcorresponding another request for whether said first address or saidanother address will be transferred first to said second switch.
 18. Themethod of claim 17, further comprising: receiving at said second switchan additional address and a corresponding additional request from anadditional device; buffering said additional address at said secondswitch prior to said transferring said second address; and arbitratingbetween said corresponding second request and said correspondingadditional request for whether said second address or said additionaladdress will be transferred first to said first switch.
 19. The methodof claim 13, wherein said delaying said corresponding first request insaid first switch includes delaying for approximately a length of timefor said requests from said second switch to arrive at said firstswitch; and wherein said delaying said corresponding second request insaid second switch includes delaying for approximately said length oftime for said requests from said first switch to arrive at said secondswitch.
 20. A system for concurrently providing addresses to a pluralityof devices, the method comprising: means for receiving at a first switcha first address and a corresponding first request from a first device;means for receiving at a second switch a second address and acorresponding second request from a second device, wherein said secondswitch is different from said first switch; means for transferring saidsecond address and said corresponding second request to said firstswitch; means for delaying said corresponding first request in saidfirst switch; means for arbitrating in said first switch between saidcorresponding first request and said corresponding second request forwhether said first address or said second address will comprise a firsttransmission; means for concurrently broadcasting to a plurality ofdevices said first transmission from said first switch and said firsttransmission from said second switch, wherein said first transmissionfrom said switch and said first transmission from said second switch areidentical.
 21. The system of claim 20, further comprising: means fortransferring said first address and said corresponding first request tosaid second switch; means for delaying said corresponding second requestin said second switch; and means for arbitrating in said second switchbetween said corresponding first request and said corresponding secondrequest for whether said first address or said second address willcomprise said first transmission.
 22. The system of claim 21, whereinsaid means for delaying said corresponding first request in said firstswitch is configured to delay for approximately a length of time forsaid requests from said second switch to arrive at said first switch;and wherein said means for delaying said corresponding second request insaid second switch is configured to delay for approximately said lengthof time for said requests from said first switch to arrive at saidsecond switch.
 23. A method of arbitrating in a first switch and asecond switch between requests to said first switch and said secondswitch, the method comprising: tracking which switch was most recentlyselected; tracking which switch is next to be selected; in response to areset, selecting the first switch; and indicting the second switch asnext to be selected; in response to only a local request to said firstswitch or only a remote request to said second switch, selecting thefirst switch; and indicting the first switch as next to be selected; inresponse to only a local request to said second switch or only a remoterequest to said first switch, selecting the second switch; and indictingthe second switch as next to be selected; in response to both a localrequest and a remote request concurrently, selecting a switch not mostrecently selected; and indicting the switch not most recently selectedas next to be selected; otherwise, selecting the first switch; andindicting the switch most recently selected as next to be selected. 24.The method of claim 23, further comprising: indicating the switch nextto be selected as the switch most recently selected upon a rising edgeof a clock.